The present invention generally relates to gate array devices, and more particularly to a gate array device having macro cells which are suited for forming a master-slave flip-flop circuit.
Recently, the demand for a gate array device is increasing because the time and cost required to develop the gate array device are reasonably small. With such an increase in the demand for the gate array device, there are new demands on the gate array device. The new demands include improved integration density and utilization efficiency of cells, a high-speed operation especially in the fields such as optical transmission and high-speed measuring instruments which use extremely high-speed (high-frequency) signals, and low noise and skew characteristics especially when supporting the high-speed operation.
FIG. 1 generally shows a conventional gate array device. The gate array device comprises a rectangular semiconductor chip 101, and terminals 102 for input/output signals and power source voltages are arranged in a peripheral portion of the chip 101. Input/output parts 104 are arranged on the inner side of the terminals 102 via interconnection regions 103. Cells exclusively for the input/or output signals are provided in the input/output parts 104. A macro cell array 105 is arranged at a central portion of the chip 101. Each macro cell of the macro cell array 105 is a unit cell which forms a logic circuit. Usually, an OR circuit, a NOR circuit, an exclusive-OR circuit, an exclusive-NOR circuit, an AND circuit, a NAND circuit or the like may be formed from one macro cell. The macro cells of the macro cell array 105 have identical constructions and are regularly arranged in a matrix arrangement. An arbitrary logic circuit can be formed by selectively connecting the macro cells by interconnections.
FIG. 2 shows an example of a signal flow within the gate array device shown in FIG. 1. Signal received at the input terminals 102 are supplied directly to the macro cell array 105 and indirectly to the macro cell array 105 through an input cell of the input/output part 104. The signals supplied to the macro cell array 105 are subjected to a logic operation, and a signal output from the macro cell array 105 is supplied to the output terminal 102 through an output cell of the input/output part 104.
Generally, the gate array device has identical macro cells which are arranged in an array, and there is no positional restrictions on a logic circuit which is to be formed in the array of macro cells. In other words, the conventional gate array device is made with priority on the degree of freedom of design so that the circuit arrangement and the interconnections may be freely designed. In addition, the conventional gate array device has a form symmetric design such that the signal input and output can be made from any terminal. Therefore, an arbitrary logic circuit can be formed anywhere within the array of macro cells.
On the other hand, from the point of view of high-speed operation, it is preferable to use one cell to realize a desired function rather than to use a plurality of cells.
For example, when a master-slave flip-flop circuit is formed from cells which can only form a basic gate, eight gates (cells) are required as may be seen from FIG. 3. But in this case, a signal passes through a plurality of gates and results in a decrease in the operation speed. In FIG. 3, the master-slave flip-flop circuit has a terminal C for receiving a clock signal, a terminal S for receiving a set signal, a terminal R for receiving a reset signal, terminals D1 and D2 for receiving two input data signals, and terminals X and X for outputting output signals of the master-slave flip-flop circuit.
Recently, there is a demand to reduce the number of cells in order to realize the high-speed operation. And in order to make it possible to form various logic circuits from one macro cell, the cell size is increasing due to an increase in the number of elements (transistors, resistors and the like) within the macro cell.
In general, the master-slave flip-flop circuit requires the largest number of elements in the gate array device. On the other hand, because a master part and a slave part of the master-slave flip-flop circuit have extremely similar constructions, there are proposals to form one master-slave flip-flop circuit from two macro cells having identical constructions.
In the master-slave flip-flop circuit, the number of elements (transistors, diodes, resistors, capacitors and the like) within the slave part is smaller than the number of elements within the master part. However, because the conventional master-slave flip-flop circuit uses two identical macro cells to constitute the slave part and the master part, a large number of elements remain unused within the macro cell which forms the slave part and the utilization efficiency of the elements within the macro cell is poor. As a result, there is a problem in that the integration density of the macro cell array as a whole cannot be improved.
On the other hand, because the conventional gate array device has the form symmetrical design as shown in FIG. 1, complex interconnections are necessary depending on the logic circuit to be formed, and the lengths of the interconnections from an input terminal to an output terminal are various and relatively long. In many cases, the complex interconnections are extremely close to each other and cross in a plan view. In such a case, the input terminal and the output terminal are often adjacent to each other and a signal interference is likely to occur between the input and output terminals.